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Advanced-control timers (TIM1&TIM8)
RM0008
Table 73.
Output control bits for complementary OCx and OCxN channels with
break feature
Control bits
Output states (1)
MOE OSSI OSSR CCxE CCxNE
bit bit bit bit bit
OCx output state
Output Disabled (not
OCxN output state
Output Disabled (not driven by
0
0
0
driven by the timer)
the timer)
OCx=0, OCx_EN=0
Output Disabled (not
OCxN=0, OCxN_EN=0
OCxREF + Polarity
0
0
1
driven by the timer)
OCxN=OCxREF xor CCxNP,
OCx=0, OCx_EN=0
OCxREF + Polarity
OCxN_EN=1
Output Disabled (not driven by
0
1
0
OCx=OCxREF xor CCxP,
the timer)
OCx_EN=1
OCREF + Polarity + dead-
OCxN=0, OCxN_EN=0
Complementary to OCREF (not
0
1
1
time
OCREF) + Polarity + dead-time
OCx_EN=1
OCxN_EN=1
1
X
Output Disabled (not
Output Disabled (not driven by
1
0
0
driven by the timer)
the timer)
OCx=CCxP, OCx_EN=0
Off-State (output enabled
OCxN=CCxNP, OCxN_EN=0
OCxREF + Polarity
1
0
1
with inactive state)
OCxN=OCxREF xor CCxNP,
OCx=CCxP, OCx_EN=1
OCxREF + Polarity
OCxN_EN=1
Off-State (output enabled with
1
1
0
OCx=OCxREF xor CCxP,
inactive state)
OCx_EN=1
OCREF + Polarity + dead-
OCxN=CCxNP, OCxN_EN=1
Complementary to OCREF (not
1
1
1
time
OCREF) + Polarity + dead-time
OCx_EN=1
OCxN_EN=1
0
0
0
0
0
0
1
1
0
1
0
1
Output Disabled (not driven by the timer)
Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP,
OCxN_EN=0
Then if the clock is present: OCx=OISx and OCxN=OISxN
after a dead-time, assuming that OISx and OISxN do not
0
1
1
1
X
0
0
1
0
1
0
correspond to OCX and OCxN both in active state.
Off-State (output enabled with inactive state)
Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,
OCxN_EN=1
Then if the clock is present: OCx=OISx and OCxN=OISxN
1
1
1
after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state
1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP
bits must be kept cleared.
Note:
310/995
The state of the external I/O pins connected to the complementary OCx and OCxN
channels depends on the OCx and OCxN channel state and the GPIO and AFIO registers.
Doc ID 13902 Rev 9
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